1. Field of the Invention
The present invention relates to semiconductor fabricating technology, and more particularly, to a silicon wafer and a method for fabricating the same.
2. Description of Related Art
In most high-voltage devices such as NMOS transistors and PMOS transistors, a well is formed to a depth of approximately 5-10 μm from a surface of a substrate generally. It is difficult to achieve a doping profile of a well having a depth of 5-10 μm only using an ion implantation process. For this reason, a dopant diffusion process should be necessarily performed using high-temperature heat treatment after the ion implantation process.
However, an oxygen precipitation is not completely achieved in a silicon bulk due to the high-temperature heat treatment. This causes crystal defects such as a ring-shaped dislocation to occur in a silicon substrate after an etching process for shallow trench isolation (STI).
In addition, these crystal defects reduce production yield, and also deteriorate electrical parameter characteristics such as a threshold voltage of a high voltage device and leakage current uniformity during a standby mode of a static random access memory (SRAM). Furthermore, these crystal defects increase a time taken to inspect and analyze lots of defects during an impurity inspection process that is inevitably performed to fabricate a semiconductor device, resulting in an increase in an overall processing time for fabricating the semiconductor device.